As large scale integration (LSI) techniques are applied to integrated circuit and hybrid circuit development, the density of circuit functions which may be performed by a single circuit chip becomes limited, not by the electronic functions which can be performed by the circuit chip, but by the packaging used to house the chip and the leads required for interconnecting the chip with other circuitry. Integrated circuits are conventionally housed in flat packs or dual in-line package (DIP) structures wherein interconnection leads are arranged in parallel rows extending from opposite sides of the chip housing. However, as the chip functions are expanded to require greater numbers of interconnection leads, standard DIP configurations pose serious limitations. For example, a sixty-eight pin array in conventional DIP packaging would require a DIP over three inches long. Because of impedance of the long leads required, such arrangements are unsuitable for high speed devices. Furthermore, such packages would consume an inordinate amount of circuit board surface area and pose problems in maintenance or replacement.
In response to the need for high density packaging for LSI devices, the industry has developed standard LSI chip carrier housings known in the art as leadless chip carriers. Conventionally, the leadless chip carrier comprises a substantially flat rectangular base piece with the circuit chip centrally located in the body of the base piece. The base piece may be plastic or ceramic. Terminal leads arranged on one or both sides of the base piece adjacent the edges are electrically connected to the circuit chip to provide electrical interconnection to external circuitry. Terminal leads may be in the form of pads or lands formed on the sides and/or edges of the base piece. Alternatively, small leg-like lead structures may extend from the edges of the base piece and be formed so that one face of each lead lies in the same plane and co-planar with or parallel with one face of the package so that the package may be surface-mounted. Often such leads are in the shape of the letter J and are conventionally referred to as J-lead packages. Similarly, such leads may also be in the form of a stretched letter S and are referred to as gullwing leads. However, since J-lead packages and gullwing packages are designed for surface mounting, i.e., attachment to a circuit board by connecting the terminal pads, J-leads or gullwing leads to circuit patterns formed on the same surface of the board on which the package is supported, such packages are conventionally referred to as leadless chip carriers even though they do have small leads extending therefrom, the term "leadless" generally having become synonymous with "surface-mounted" in this regard.
As packages for circuit chips become more compact, the difficulties in holding such packages in such a manner as to make electrical contact with the terminals without damaging the package or the terminals while subjecting the packaged device to burn-in and testing procedures become even more complicated. Various leadless chip carriers have been adopted as industry standards and test sockets designed to accommodate each device package. The industry standard for leadless chip carrier sockets is described, for example, in U.S. Pat. No. 4,191,377 which issued to Wayne K. Pfaff on Jan. 1, 1985.
With the advent of J-lead and gullwing devices, particularly such devices in large pin count configurations, it has become increasingly difficult to make and maintain electrical contact between each of the package terminal leads and the contact pins of the test socket under the adverse conditions encountered in burn-in and testing. Not only do large pin count packages require smaller terminal leads, thus dictating higher accuracy in contact pin alignment, the force required to open a large number of normally closed contacts is directly proportional to the number of contact pins. Furthermore, as pin count increases, the terminal leads become smaller, more delicate and thus more likely to become damaged or bent during testing.